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| MOTOROLA (Parts Not Suitable for New Designs) Order this document by MC68307/D SEMICONDUCTOR TECHNICAL INFORMATION MC68307 MC68307V Technical Summary Integrated Multiple-Bus Processor The MC68307 is an integrated processor combining a static 68EC000 processor with multiple interchip bus interfaces. The MC68307 is designed to provide optimal integration and performance for applications such as digital cordless telephones, portable measuring equipment, and point-of-sale terminals. By providing 3.3 V, static operation in a small package, the MC68307 delivers cost-effective performance to handheld, batterypowered applications. The MC68307 (shown in Figure 1) contains a static EC000 core processor, multiple bus interfaces, a serial channel, two timers, and common system glue logic. The multiple bus interfaces include: dynamic 68000 bus, 8051 bus, and Motorola bus (M-bus) or I2C bus1. The dynamically sized 68000 bus allows 16-bit performance out of static random access memory (SRAM) while still providing a low-cost interface to an 8-bit read-only memory (ROM). The 8051 bus interfaces gluelessly to 8051-type devices and allows the reuse of applicationspecific integrated circuits (ASICs) designed for this industry standard bus. The M-bus is an industry standard 2-wire interface which provides efficient communications with peripherals such as EEPROM, analog/digital (A/ D) converters, and liquid crystal display (LCD) drivers. Thus, the MC68307 interfaces gluelessly to boot ROM, SRAM, 8051 devices, M-bus devices, and memory-mapped peripherals. The MC68307 also incorporates a slave mode which allows the EC000 core to be turned off, providing a 3.3-V static, low-power multi-function peripheral for higher performance M68000 family processors. SYSTEM INTEGRATION MODULE (SIM07) 8/16-BIT M68000 BUS INTERFACE 8051 BUS INTERFACE CHIP SELECT AND DTACK INTERRUPT CONTROLLER PROCESSOR CONTROL, CLOCK AND LOW POWER SYSTEM PROTECTION PARALLEL I/O PORTS JTAG PORT DUAL TIMER MODULE STATIC EC000 CORE PROCESSOR DYNAMIC BUS SIZING EXTENSION 68000 INTERNAL BUS M-BUS MODULE UART SERIAL I/O Figure 1. MC68307 Block Diagram 1. I2C bus is a proprietary Philips interface bus. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) MOTOROLA, 1993 Thi d t t d ith F Mk 402 The main features of the MC68307 include: * Static EC000 Core Processor--Identical to MC68EC000 Microprocessor -- Full compatibility with MC68000 and MC68EC000 -- 24-bit address bus, for 16-Mbyte off-chip address space -- 16-bit on-chip data bus for MC68000 bus operations -- Static design allows processor clock to be stopped providing dramatic power savings -- 2.4 MIPS performance at 16.67-MHz processor clock * External M68000 Bus Interface with Dynamic Bus Sizing for 8-bit and 16-bit Data Ports * External 8-Bit Data Bus Interface (8051-Compatible) * M-Bus Module -- Provides interchip bus interface for EEPROMs, LCD controllers, A/D converters, etc. -- Compatible with industry-standard I2C bus -- Master or slave operation modes, supports multiple masters -- Automatic interrupt generation with programmable level -- Software-programmable clock frequency -- Data rates from 4-100 Kbit/s above 3.0-MHz system clock * Universal Asynchronous Receiver/Transmitter (UART) Module -- Flexible baud rate generator -- Based on MC68681 Dual Universal Asynchronous Receiver/Transmitter (DUART) programming model -- 5 Mbits/s maximum transfer rate at 16.67-MHz system clock -- Automatic interrupt generation with programmable level -- Modem control signals available (CTS,RTS) * Timer Module -- Dual channel 16-bit general purpose counter/timer -- Multimode operation, independent capture/compare registers -- Automatic interrupt generation with programmable level -- Third 16-bit timer configured as a software watchdog -- 60-ns resolution at 16.67-MHz system clock -- Each timer has an input and an output pin * System Integration Module (SIM07), Incorporating Many Functions Typically Relegated to External Programmable Array Logic (PALs), Transistor-Transistor Logic (TTL), and ASICs, such as: -- System configuration, programmable address mapping -- System protection by hardware watchdog logic -- Power-down mode control, programmable processor clock driver -- Four programmable chip selects with wait state generation logic -- Three simple peripheral chip selects -- Parallel input/output ports, some with interrupt capability -- Programmed interrupt vector response for on-chip peripheral modules -- IEEE 1149.1 boundary scan test access port (JTAG) * Operation from DC to 16.67 MHz (Processor Clock) * Operating Voltages of 3.3V 0.3V and 5V 0.5V * Compact 100-Lead Quad Flat Pack (QFP) Package 2 MC68307 TECHNICAL INFORMATION MOTOROLA M68300 FAMILY The MC68307 is one of a series of components in Motorola's M68300 family. Other members of the family include the MC68302, MC68306, MC68330, MC68331, MC68332, MC68F333, MC68334, MC68340, MC68341, MC68349, and MC68360. ORGANIZATION The M68300 family of integrated processors and controllers is built on an M68000 core processor and a selection of intelligent peripherals appropriate for a set of applications. Common system glue logic such as address decoding, wait state insertion, interrupt prioritization, and watchdog timing is also included. Each member of the M68300 family is distinguished by its selection of on-chip peripherals. Peripherals are chosen to address specific applications but are often useful in a wide variety of applications. The peripherals may be highly sophisticated timing or protocol engines that have their own processors, or they may be more traditional peripheral functions, such as UARTs and timers. ADVANTAGES By incorporating so many major features into a single M68300 family chip, a system designer can realize significant savings in design time, power consumption, cost, board space, pin count, and programming. The equivalent functionality can easily require 20 separate components. Each component might have 16-64 pins, totaling over 350 connections. Most of these connections require interconnects or are duplications. Each connection is a candidate for a bad solder joint or misrouted trace. Each component is another part to qualify, purchase, inventory, and maintain. Each component requires a share of the printed circuit board. Each component draws power, which is often used to drive large buffers to get the signal to another chip. The cumulative power consumption of all the components must be available from the power supply. The signals between the central processing unit (CPU) and a peripheral might not be compatible nor run from the same clock, requiring time delays or other special design considerations. In an M68300 family component, the major functions and glue logic are all properly connected internally, timed with the same clock, fully tested, and uniformly documented. Only essential signals are brought out to pins. The primary package is the surface-mount plastic QFP for the smallest possible footprint. MOTOROLA MC68307 TECHNICAL INFORMATION 3 MC68307 ARCHITECTURE To improve total system throughput and reduce part count, board size and cost of system implementation, the MC68307 integrates a powerful processor, intelligent peripheral modules, and typical system interface logic. These functions include the SIM07, timers, UART, M-bus interface, and 8051-compatible bus interface. The EC000 processor core communicates with these modules via an internal bus, providing the opportunity for fully synchronized communication between all modules and allowing interrupts to be handled in parallel with data transfers, greatly improving system performance. STATIC EC000 CORE The EC000 core is a core implementation of the MC68000 32-bit microprocessor architecture. The features of the EC000 core processor include: * Low power, static HCMOS implementation * 24-bit address bus, 16-bit data bus * Seventeen 32-bit data and address registers * 56 powerful instruction types that support high level development languages * 14 addressing modes and five main data types * Seven priority levels for interrupt control The EC000 core is completely upward user code-compatible with all other members of the M68000 microprocessor families and thus has access to a broad base of established real-time kernels, operating systems, languages, applications, and development tools. EC000 Core Programming Model The EC000 core offers sixteen 32-bit registers and a 32-bit program counter (see Figure 2). The first eight registers (D7-D0) are used as data registers for byte (8-bit), word (16-bit) and long-word (32-bit) operations. Because the use of the data registers will affect the condition code register (indicating negative number, carry, and overflow conditions) they are primarily used for data manipulation. The second set of seven registers (A6- A0) and the user stack pointer (USP) may be used as software stack pointers and base address registers. These registers can be used for word and long-word operations and do not affect the condition code register. All of the registers (D7-D0 and A6-A0) may be used as index registers. In supervisor mode, the upper byte of the status register (SR) and the supervisor stack pointer (SSP) are also available to the programmer. These registers are shown in Figure 3. The SR (refer to Figure 4) contains the interrupt mask (seven levels available) as well as the following condition codes: extend (X), negative (N), zero (Z), overflow (V), and carry (C). Additional status bits indicate whether the processor is in trace mode (T-bit) and in supervisor or user state (S-bit). 4 MC68307 TECHNICAL INFORMATION MOTOROLA 31 16 15 87 0 D0 D1 D2 D3 D4 D5 D6 D7 DATA REGISTERS 31 16 15 0 A0 A1 A2 A3 A4 A5 A6 ADDRESS REGISTERS 31 16 15 0 A7 (USP) USER STACK POINTER 31 0 PC 7 0 CCR STATUS REGISTER PROGRAM COUNTER Figure 2. User Programming Model Figure 3. Supervisor Programming Model Supplement SYSTEM BYTE 15 T TRACE MODE SUPERVISOR STATE INTERRUPT MASK 13 S 10 I2 I1 8 I0 USER BYTE 4 X N Z V 0 C CONDITION CODES EXTEND NEGATIVE ZERO OVERFLOW CARRY Figure 4. Status Register MOTOROLA MC68307 TECHNICAL INFORMATION 5 Data Types and Addressing Modes Five basic data types are supported: 1.) Bits 2.) Binary coded decimal (BCD) digits (4 bits) 3.) Bytes (8 bits) 4.) Words (16 bits) 5.) Long words (32 bits) In addition, operations on other data types such as memory addresses, status word data, etc. are provided in the instruction set. The 14 addressing modes listed in Table 1 include six basic types: 1.) Register direct 2.) Register indirect 3.) Absolute 4.) Program counter relative 5.) Immediate 6.) Implied Included in the register indirect addressing modes is the capability to perform postincrementing, predecrementing, offsetting, and indexing. The program counter relative mode can also be modified via indexing and offsetting. Instruction Set Overview The EC000 core instruction set is listed in Table 2. The instruction set facilitates ease of programming by supporting high-level languages. Each instruction, with few exceptions, operates on bytes, words, and longwords, and most instructions can use any of the 14 addressing modes. Combining instruction types, data types, and addressing modes, over 1000 useful instructions are provided. These instructions include signed and unsigned, multiply and divide, quick arithmetic operations, BCD arithmetic, and expanded operations (through traps). 6 MC68307 TECHNICAL INFORMATION MOTOROLA Table 1. Addressing Modes Addressing modes Register direct addressing Data register direct Address register direct Absolute data addressing Absolute short Absolute long Program counter relative addressing Relative with offset Relative with index offset Register indirect addressing register Register indirect Postincrement register indirect Predecrement register indirect Register indirect with offset Indexed register indirect with offset Syntax Dn An xxx.W xxx.L d16(PC) d8(PC, Xn) (An) (An)+ -(An) d16(An) d8(An, Xn) Immediate data addressing Immediate #xxx Quick immediate #1-#8 Implied addressing Implied register SR/USP/SP/PC Legend: Dn = Data Register An = Address Register Xn = Address or Data Register Used as Index Register SR = Status Register PC = Program Counter SP = Stack Pointer USP = User Stack Pointer <> = Effective Address d8 = 8-Bit Offset (Displacement) d16 = 16-Bit Offset (Displacement) #xxx = Immediate Data MOTOROLA MC68307 TECHNICAL INFORMATION 7 Table 2. Instruction Set Mnemonic ABCD ADD ADDA ADDQ ADDI ADDX AND ANDI ANDI to CCR ANDI to SR ASL ASR Bcc BCHG BCLR BRA BSET BSR BTST CHK CLR CMP CMPA CMPM CMPI DBcc DIVS DIVU EOR EORI EORI to CCR EORI to SR EXG EXT JMP JSR LEA LINK LSL LSR MOVE MOVEA Description Mnemonic Add decimal with extend MOVEM Add MOVEP Add address MOVEQ Add quick MOVE from SR Add immediate MOVE to SR Add with extend MOVE to CCR Logical AND MOVE USP AND immediate MULS AND immediate to condition codes MULU AND immediate to status register NBCD Arithmetic shift left NEG Arithmetic shift right NEGX Branch conditionally NOP Bit test and change NOT Bit test and clear OR Branch always ORI Bit test and set ORI to CCR Branch to subroutined set ORI to SR Bit test PEA Check register against bounds RESET Clear operand ROL Compare ROR Compare address ROXL Compare memory ROXR Compare immediate RTE Test cond, decrement and branch RTR Signed divide RTS Unsigned divide SBCD Exclusive OR Scc Exclusive OR immediate STOP Exclusive OR immediate to condition codes SUB Exclusive OR immediate to status register SUBA Exchange registers SUBI Sign extend SUBQ Jump SUBX Jump to subroutine SWAP Load effective address TAS Link stack TRAP Logical shift left TRAPV Logical shift right TST Move UNLK Move address -- Description Move multiple registers Move peripheral data Move quick Move from status register Move to status register Move to condition codes Move user stack pointer Signed multiply Unsigned multiply Negate decimal with extend Negate Negate with extend No operation Ones complement Logical OR OR immediate OR immediate to condition codes OR immediate to status register Push effective address Reset external devices Rotate left without extend Rotate right without extend Rotate left with extend Rotate right with extend Return from exception Return and restore Return from subroutine Subtract decimal with extend Set conditional Stop Subtract Subtract address Subtract immediate Subtract quick Subtract with extend Swap data register halves Test and set operand Trap Trap on overflow Test Unlink -- 8 MC68307 TECHNICAL INFORMATION MOTOROLA SYSTEM INTEGRATION MODULE The MC68307 system integration module (SIM07) consists of several functions that control the system start-up, initialization, configuration, and the external bus with a minimum of external devices. The SIM07 features include: * System configuration * Oscillator & clock dividers * Reset control, power-down mode control * Chip-selects and wait states * External bus interfaces, 68000 and 8051-compatible * Parallel input/outputs with interrupt capability * Interrupt configuration/response * Software watchdog * JTAG test access port System Configuration The MC68307 system configuration logic consists of a module base address register (MBAR) and a system control register (SCR) which together allow the user to configure operation of the following functions: * Base address and address space of internal peripheral registers * Low-power (stand-by) modes * Hardware watchdog for system protection * 8051-compatible bus * Peripheral chip selects * Data bus size control for chip selected address ranges Chip Select Logic and Dynamic Bus Sizing The MC68307 provides four programmable chip-select signals (CS3-CS0). For a given chip-select block, the user may choose whether the chip-select allows read-only, write-only, or both read and write accesses, whether the chip-select should match only one function code value or all values, whether a DTACK is automatically generated for this chip-select, and after how many wait states (from zero to six) the DTACK will be generated. Each of the chip selects includes a dynamic bus-sizing extension to the basic 68000 bus which allows the system designer to mix 16-bit and 8-bit contiguous address memory devices (RAM, ROM) on a 16-bit data bus system. An additional feature of CS2 allows the user to opt either to use the programmable chip select CS2 or to use four peripheral chip selects (CS2A, CS2B, CS2C, and CS2D). When the four peripheral chip selects are enabled, each one selects a16-Kbyte block within the programmed range of CS2. MOTOROLA MC68307 TECHNICAL INFORMATION 9 External Bus Interface The external bus interface handles the transfer of information between the internal EC000 core and the memory, peripherals, or other processing elements in the external address space. It consists of a 68000 bus interface and an 8051-compatible bus interface. The external 68000 bus provides up to 24 address lines and 16 data lines. Each bus access can appear externally either as a 68000 bus cycle (either 16-bit or 8-bit dynamic data bus width) or as an 8-bit wide 8051-compatible bus cycle (multiplexing 8 bits of address and data) with the appropriate sets of control signals. Parallel General-Purpose I/O Ports The MC68307 supports two general-purpose I/O ports, port A (8-bits) and port B (16-bits), whose pins can be configured as general-purpose I/O pins or as dedicated peripheral interface pins for the on-chip modules. Each port pin can be independently programmed as general-purpose I/O pins, even when other pins related to the same on-chip peripheral are used as dedicated pins. Even if all the pins for a particular peripheral are configured as general-purpose I/O, the peripheral will still operate normally (although this is only useful in the case of the timer module). Power consumption may be reduced by turning off unused modules. Interrupt Controller The interrupt controller supports interrupts from three sources. The first source is an external, nonmaskable interrupt input on the IRQ7 signal, which always causes an interrupt priority level 7 request to the EC000 core. Assuming no other source is programmed as a level 7 source, this input will always obtain the immediate attention of the core. The second source is an external interrupt received through the 8-channel latched interrupt port (INT8-INT1). Each INTx signal can be programmed with an interrupt priority level, and each can have pending interrupts cleared independently of the others. The third source of interrupts is the on-chip peripherals. The interrupt controller allows the user to assign the interrupt priority level each of the four on-chip peripherals will use, and to determine a particular vector number to be presented when the respective module receives an interrupt acknowledge from the processor via the interrupt controller logic. Software Watchdog A software watchdog timer is used to protect against system failures by providing a means to escape from unexpected input conditions, external events, or programming errors. Once started, the software watchdog timer must be cleared by software on a regular basis so that it never reaches its time-out value. Upon reaching the time-out value, the assumption is made that a system failure has occurred, and the software watchdog logic resets the MC68307. 10 MC68307 TECHNICAL INFORMATION MOTOROLA Low-Power Stop Logic Various options for power-saving are available: turning off unused peripherals, reducing processor clock speed, disabling the processor altogether or a combination of these. A wake-up from power-down can be achieved by causing an interrupt at the interrupt controller logic which runs throughout the period of processor power-down. Any interrupt will cause a wake-up of the EC000 core followed by processing of that interrupt. The on-chip peripherals can initiate a wake-up; for example, the timer can be set to wake-up after a certain elapsed time, or number of external events, or the UART can cause a wake-up on receiving serial data. The clocks provided to the various internal modules can all be disabled to further reduce power consumption. In the case of the UART, its clock is restarted automatically by a transition on the RxD pin, so that incoming data is clocked in. When the data has been completely received, an interrupt from the UART wakes-up the processor core. If the other on-chip peripherals (the timer and M-bus) are required to cause a wake-up, then their clocks should not be disabled in this manner. JTAG Test Access Port To aid in system diagnostics the MC68307 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (joint test action group). SIM07 Programming Model The SIM07 programming model is listed in Tables 3-7. The FC (function code) column in each table indicates whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user space (S/U). With the exception of the system configuration registers (listed in Table 3), the address column of each table contains the offset from the base address (MBASE) contained in the MBAR. Table 3. SIM07 System Configuration Registers Address $0000F0 $0000F2 $0000F4 $0000F6 $0000F8 $0000FA $0000FC $0000FE FC -- S S S -- -- -- -- Register Name Reserved--No external bus access Module Base Address Register (MBAR) System Control Register (SCR) System Control Register (SCR) Reserved--No external bus access Reserved--No external bus access Reserved--No external bus access Reserved--No external bus access MOTOROLA MC68307 TECHNICAL INFORMATION 11 Table 4. SIM07 Chip Select Registers Address MBASE+$040 MBASE+$042 MBASE+$044 MBASE+$046 MBASE+$048 MBASE+$04A MBASE+$04C MBASE+$04E FC S/U S/U S/U S/U S/U S/U S/U S/U Register Name Base register 0 Option register 0 Base register 1 Option register 1 Base register 2 Option register 2 Base register 3 Option register 3 Table 5. SIM07 External Bus Interface Registers Address MBASE+$011 MBASE+$013 MBASE+$015 MBASE+$016 MBASE+$018 MBASE+$01A FC S/U S/U S/U S/U S/U S/U Register Name Do not access byte $010 Port A control register (PACNT) Do not access byte $012 Port A data direction register (PADDR) Do not access byte $014 Port A data register (PADAT) Port B control register (PBCNT) Port B data direction register (PBDDR) Port B data register (PBDAT) Table 6. SIM07 Interrupt Controller Registers Address MBASE+$020 MBASE+$022 MBASE+$024 MBASE+$027 FC S/U S/U S/U S/U Register Name Latched interrupt control register 1 (LICR1) Latched interrupt control register 2 (LICR2) Peripheral interrupt control register (PICR) Do not access byte $026 Programmable interrupt vector register (PIVR) Table 7. SIM07 Software Watchdog Registers Address MBASE+$12A MBASE+$12C FC S/U S/U Register Name Watchdog reference register (WRR) Watchdog counter register (WCR) 12 MC68307 TECHNICAL INFORMATION MOTOROLA DUAL TIMER MODULE The MC68307 includes two independent, identical, general-purpose timers. Each general-purpose timer block contains a free-running 16-bit timer which can be used in various modes, to capture the timer value with an external event, to trigger an external event or interrupt when the timer reaches a set value, or to count external events. Each has an 8-bit prescaler to allow programmable clock input frequency derived from the system clock (divided by 1 or by 16) or external count input. The output pins (one per timer) have a variety of programmable modes and the output signal can be an active-low pulse or a toggle of the current output. The features of the 16-bit timer include: * Maximum period of 16 seconds (at 16.67 MHz) * 60-ns resolution (at 16.67 MHz) * Programmable sources for the clock input, including external clock * Input capture capability with programmable trigger edge on input pins * Output compare with programmable mode for the output pins * Two timers externally cascadeable to form a 32-bit timer * Free-run and restart modes Dual Timer Programming Model Table 8 shows the programming model for the dual timer module. The FC (function code) column indicates whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user space (S/U). The address column contains the offset from the base address (MBASE) contained in the SIM07 MBAR. Table 8. Dual Timer Module Registers Address MBASE+$120 MBASE+$122 MBASE+$124 MBASE+$126 MBASE+$129 MBASE+$130 MBASE+$132 MBASE+$134 MBASE+$136 MBASE+$139 FC S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U Register Name Timer mode register 1 (TMR1) Timer reference register 1 (TTR1) Timer capture register 1 (TCR1) Timer counter 1 (TCN1) Do not access byte $128 Timer event register 1 (TER1) Timer mode register 2 (TMR2) Timer reference register 2 (TRR1) Timer capture register 2 (TCR2) Timer counter 2 (TCN2) Do not access byte $138 Timer event register 2 (TER2) MOTOROLA MC68307 TECHNICAL INFORMATION 13 M-BUS INTERFACE MODULE The M-bus is a two-wire, bidirectional serial bus which provides a simple and efficient means of data exchange between devices; it is fully compatible with the I2C bus standard. The maximum data rate is limited to 100 kbit/s at 16.67-MHz system clock speed. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. The serial bit clock frequency of the M-bus is programmable and ranges from 3830 Hz to 757 kHz for a 16.67-MHz internal operating frequency. The M-bus system is a true multimaster bus including collision detection and arbitration to prevent data corruption (when two or more masters intend to control the bus simultaneously). The M-bus system uses the SDA and SCL signals for data transfer. All devices connected to the M-bus interface must have open-drain or open-collector output; a logic AND function is exercised in both lines with pull-up resistors. The features of the M-bus include: * Fully compatible with I2C bus standard * Multimaster operation * Software programmable for one of 32 different serial clock frequencies * Software selectable acknowledge bit * Interrupt driven byte-by-byte data transfer * Arbitration-lost driven interrupt with automatic mode switching from master to slave * Calling address identification interrupt * Generate/detect the START or STOP signal * Repeated START signal generation * Generate/recognize the acknowledge bit * Bus busy detection M-Bus Programming Model The programming model for the M-bus module is listed in Table 9. The FC (function code) column indicates whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user space (S/U). The address column contains the offset from the base address (MBASE) contained in the SIM07 MBAR. Table 9. M-Bus Module Registers Address MBASE+$141 MBASE+$143 MBASE+$145 MBASE+$147 MBASE+$149 FC S/U S/U S/U S/U S/U Register Name Do not access byte $140 M-bus address register (MADR) Do not access byte $142 M-bus frequency divider register (MFDR) Do not access byte $144 M-bus control register (MBCR) Do not access byte $146 M-bus status register (MBSR) Do not access byte $148 M-bus data I/O register (MBDR) 14 MC68307 TECHNICAL INFORMATION MOTOROLA UART MODULE The UART module in the MC68307 is based on the MC68681 DUART, which is part of the M68000 family of peripherals which directly interfaces to the MC68000 processor via an asynchronous bus structure. The UART module consists of internal control logic, timing and baud-rate generator logic, interrupt control logic, and the serial communications channel. Only one serial channel is implemented for the MC68307. Clocking is provided by the MC68307 system clock, via a programmable prescaler. This allows various baud rates to be chosen. Modem support is provided with request-to-send (RTS) and clear-to-send (CTS) signals available. The serial port can sustain data rates of 5Mbits/s. The features of the UART include: * Full-duplex asynchronous/synchronous receiver/transmitter channels * Maximum data transfer: 1X clock--5 Mbits/s, 16X clock--625 Kbits/s * Quadruple-buffered receiver data registers * Double-buffered transmitter data registers * Programmable baud rate for serial channel -- User defined rate derived from a programmable timer * Programmable data format -- Five to eight data bits plus parity -- Odd, even, no parity, or force parity -- One, one and one-half, or two stop bits programmable in 1/16 bit increments * Programmable channel modes for diagnostics -- Normal (full duplex)/automatic echo/local loopback/remote loopback * Automatic wake-up mode for multidrop applications * Versatile interrupt system -- Single interrupt output with eight maskable interrupting conditions -- Interrupt vector output on interrupt acknowledge * Parity, framing, and overrun error detection * False-start bit detection * Line-break detection and generation * Detects break which originates in the middle of a character * Interrupt or poll on start/stop break MOTOROLA MC68307 TECHNICAL INFORMATION 15 UART Programming Model The programming model for the UART module is listed in Table 10. The FC (function code) column indicates whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user space (S/U). The address column contains the offset from the base address (MBASE) contained in the SIM07 MBAR. Table 10. UART Module Registers Address MBASE+$101 MBASE+$103 MBASE+$105 MBASE+$107 MBASE+$107 MBASE+$109 MBASE+$109 MBASE+$10B MBASE+$10B MBASE+$10D MBASE+$10F MBASE+$119 MBASE+$11B MBASE+$11D MBASE+$11F FC S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U Register Name Do not access byte $100 UART mode register (UMR1,UMR2) Do not access byte $102 UART status/clock select register (USR,UCSR) Do not access byte $104 UART command register (UCR) Do not access byte $106 (read) UART receive buffer (UTB, URB) Do not access byte $106 (write) UART transmit buffer (UTB, URB) Do not access byte $108 (read) UART CTS change register (UCCR) Do not access byte $108 (write) UART auxiliary control register (UACR) Do not access byte $10A (read) UART interrupt status register (UISR) Do not access byte $10A (write) UART interrupt mask register (UIMR) Do not access byte $10C Baud rate gen prescaler msb (UBG1) Do not access byte $10E Baud rate gen prescaler lsb (UBG2) Do not access byte $118 UART interrupt vector register (UIVR) Do not access byte $11A UART CTS unlatched input port (UCP) Do not access byte $11C UART RTS output bit set cmd (URBS) Do not access byte $11E UART RTS output bit reset cmd (URBR) 16 MC68307 TECHNICAL INFORMATION MOTOROLA EXTERNAL SIGNAL DESCRIPTIONS Figure 5 shows the MC68307 input and output signals in their respective functional groups. Table 11 briefly describes each of the MC68307 signals. TDO TDI TMS TCK CS2B/PA0 CS2C/PA1 CS2D/PA2 TOUT1/PA3 TOUT2/PA4 BR/PA5 BG/PA6 BGACK/PA7 MULTIPLEXED PARALLEL I/O 6 6 VCC GND AS UDS LDS R/W DTACK JTAG PORT 8-/16-BIT 68000 BUS INTERFACE INTERRUPT CONTROLLER STATIC EC000 CORE PROCESSOR D15-D0 A23-A8 DYNAMIC BUS SIZING EXTENSION SYSTEM INTEGRATION MODULE (SIM07) AD7-AD0 /A7-A0 RD WR ALE CS3 CS2/CS2A CS1 CS0 BUSW IRQ7 RESET HALT TRST/RSTIN 8051 BUS INTERFACE 68000 INTERNAL BUS CHIP SELECT AND DTACK PROCESSOR CONTROL, CLOCK AND LOW POWER M-BUS (I2C) MODULE UART SERIAL I/O DUAL TIMER MODULE EXTAL XTAL CLKOUT TXD/PB2 RXD/PB3 RTS/PB4 CTS/PB5 TIN1/PB6 INT1/PB8 INT2/PB9 INT3/PB10 INT4/PB11 INT5/PB12 INT6/PB13 INT7/PB14 INT8/PB15 MULTIPLEXED PARALLEL I/O Figure 5. MC68307 Detailed Block Diagram MOTOROLA MC68307 TECHNICAL INFORMATION TIN2/PB7 SCL/PB0 SDA/PB1 17 Table 11. Signal index Mnemonic D15-D0 A23-A8 AD7-AD0/A7-A0 AS UDS LDS R/W DTACK HALT RESET TRST/RSTIN CS0 CS1 CS2/CS2A CS3 ALE RD WR EXTAL XTAL CLKOUT BUSW CS2B/PA0 CS2C/PA1 CS2D/PA2 TOUT1/PA3 TOUT2/PA4 BR/PA5 BG/PA6 BGACK/PA7 IRQ7 SCL/PB0 SDA/PB1 TxD/PB2 RxD/PB3 RTS/PB4 CTS/PB5 TIN1/PB6 TIN2/PB7 INT1/PB8 INT2/PB9 INT3/PB10 INT4/PB11 INT5/PB12 INT6/PB13 INT7/PB14 INT8/PB15 Description Data bus Address bus out Multiplexed 8051 address/data/Address bus out Address strobe Upper data strobe Lower data strobe Read/write Data acknowledge System halt System reset Power-on reset Chip select 0 (ROM) Chip select 1 (RAM) Chip select 2 (peripherals) Chip select 3 (8051) Address latch enable (8051) 8051-bus read 8051-bus write External clock/crystal in External crystal Clock to system Initial data bus width for CS0 Chip select 2B / I/O port A bit 0 Chip select 2C / I/O port A bit 1 Chip select 2D / I/O port A bit 2 Timer 1 output / I/O port A bit 3 Timer 2 output / I/O port A bit 4 Bus request input / I/O port A bit 5 Bus grant output / I/O port A bit 6 Bus grant acknowledge output / I/O port A bit 7 Interrupt level 7 Serial M-bus clock / port B bit 0 Serial M-bus data / port B bit 1 UART transmit data / port B bit 2 UART receive data / port B bit 3 Request-to-send / port B bit 4 Clear-to-send / port B bit 5 Timer 1 input / port B bit 6 Timer 2 input / port B bit 7 Interrupt in 1 / port B bit 8 Interrupt in 2 / port B bit 9 Interrupt in 3 / port B bit 10 Interrupt in 4 / port B bit 11 Interrupt in 5 / port B bit 12 Interrupt in 6 / port B bit 13 Interrupt In 7 / port B bit 14 Interrupt in 8 / port B bit 15 Configuration Bidirectional Output Bidirectional Output Output Output Output Bidirectional Bidirectional Bidirectional Input Output Output Output Output Output Output Output Input Output Output Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 18 MC68307 TECHNICAL INFORMATION MOTOROLA ELECTRICAL CHARACTERISTICS PRELIMINARY DC ELECTRICAL SPECIFICATIONS Characteristic Input high voltage (except clock) Input low voltage Clock input high voltage Input leakage current @5.25V (all input-only Three-state (off state) input current @2.4V/0.4V Output high voltage (IOH = rated maximum) Output low voltage (IOL = rated maximum) Current dissipation VCC = 5.0V0.5Vb VCC = Low power STOP mode VCC = 5.0V0.5V VCC = 3.3V0.3V Power dissipation VCC = 5.0V0.5V VCC = 3.3V0.3V Input capacitancec All input-only pins All I/O pins Load capacitancec All output pins (except SCL and SDA) SCL, SDA a. Not including internal pull-up or pull-down. b. Currents listed are with no loading. c. Capacitance is periodically sampled rather than 100% tested. 3.3V0.3Vb fEXT = 16.67MHz fEXT = 8MHz fEXT = 16.67MHz fEXT = 8MHz fEXT = 16.67MHz fEXT = 8MHz PD pins)a Symbol VIH VIL VIHC IIN ITSI VOH VOL ID Min 2.0 GND 0.7 VCC - 2.5 -- VCC - 0.75 -- -- -- -- -- Max VCC 0.8 VCC + 0.3 2.5 20 -- 0.5 30 TBD TBD TBD Unit V V V A A V V mA -- -- -- -- -- -- 0.26 TBD 10 20 100 400 W CIN pF CL pF AC ELECTRICAL SPECIFICATION DEFINITIONS The AC specifications presented consist of output delays, input setup and hold times and signal skew times. All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals. The measurement of the AC specifications is defined by the waveforms shown in Figure 6. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in the figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown. Inputs are specified with minimum setup and hold times, and are measured as shown. Finally, the measurement for signal-to-signal specifications are shown. Note that the testing levels used to verify conformance to the AC specifications does not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics. MOTOROLA MC68307 TECHNICAL INFORMATION 19 DRIVE TO 2.4 V 2.0 V CLK 0.8 V DRIVE TO 0.5 V OUTPUTS(1) CLK VALID OUTPUT n A B 2.0 V 0.8 V 2.0 V 0.8 V VALID OUTPUT 0.8 V 2.0 V n+1 B A OUTPUTS(2) CLK VALID OUTPUT n 2.0 V 0.8 V 2.0 V 0.8 V VALID OUTPUT n+1 C DRIVE TO 2.4 V DRIVE TO 0.5 V 2.0 V 0.8 V D 2.0 V 0.8 V INPUTS(3) CLK VALID INPUT C 2.0 V 0.8 V D 2.0 V 0.8 V DRIVE TO 2.4 V DRIVE TO 0.5 V INPUTS(4) CLK VALID INPUT ALL SIGNALS(5) 2.0 V 0.8 V E F 2.0 V 0.8 V NOTES: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. This output timing is applicable to all parameters specified relative to the falling edge of the clock. 3. This input timing is applicable to all parameters specified relative to the rising edge of the clock. 4. This input timing is applicable to all parameters specified relative to the falling edge of the clock. 5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal. LEGEND: A. Maximum output delay specification. B. Minimum output hold time. C. Minimum input setup time specification. D. Minimum input hold time specification. E. Signal valid to signal valid specification (maximum or minimum). F. Signal valid to signal invalid specification (maximum or minimum). Figure 6. Drive Levels and Test Points for AC Specifications 20 MC68307 TECHNICAL INFORMATION MOTOROLA PRELIMINARY AC ELECTRICAL SPECIFICATIONS--CONTROL TIMING (See Figure 7) Num Frequency of operation Cycle time Clock pulse width Clock rise and fall time Characteristic 3.3 V 8 MHz Min Max 0.0 8.33 120 -- 54 -- -- 5 5V 16.67 MHz Min Max 0.0 16.67 60 -- 27 -- -- 5 Unit MHz ns ns ns 1 2,3 4,5 1 2 2.0 V 0.8 V 4 5 3 NOTE: Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 V and 2.0 V. Figure 7. Clock Timing . MOTOROLA MC68307 TECHNICAL INFORMATION 21 PRELIMINARY AC TIMING SPECIFICATIONS (VCC = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc; TA = TL to TH) (See Figures 8-10) Num 6 7 8 9a 11b 12a 13b 14b 14Ab 15b 17c 18a 20 20Ac 21b 22c 23 25b 26b 27d 28b 29 29A 30 31 32 33 34 35 36 37 38 39 46 47d 53 Characteristic Clock low to address valid Clock high to address, data bus high impedance (maximum) Clock high to address (minimum) Clock high to AS, CSx, LDS, UDS asserted Address valid to AS, CSx, LDS, UDS asserted (read) / AS, CSx asserted (write) Clock low to AS, CSx, LDS, UDS negated AS, CSx, LDS, UDS negated to address, FC invalid AS, CSx, (and LDS, UDS read) width asserted LDS, UDS width asserted AS, CSx, LDS, UDS width negated AS, CSx, LDS, UDS negated to R/W invalid Clock high to R/W high (read) Clock high to R/W low (write) AS, CSx, asserted to R/W low (write) Address valid to R/W low (write) R/W low to LDS, UDS asserted (write) Clock low to data-out valid (write) AS, CSx, LDS, UDS negated to data-out invalid (write) Data-out valid to LDS,UDS asserted (write) Data-in valid to clock low (setup time on read) AS, CSx, LDS, UDS negated to DTACK negated (asynchronous hold) AS, CSx, LDS, UDS negated to data-in invalid (hold time on read) AS, CSx, LDS, UDS negated to data-in high impedance AS, CSx, LDS, UDS negated to BR negated DTACK asserted to data-in valid (setup time) HALT and RESET input transition time Clock high to BG asserted Clock high to BG negated BR asserted to BG asserted BR negated to BG negated BGACK asserted to BG asserted BG asserted to control, address, data bus high impedance (AS, CSx negated) BG width negated BGACK width low Asynchronous input setup time Data-out hold from clock high 3.3V 8.33 MHz Min Max -- 60 -- 100 0 -- 3 60 30 -- 3 30 240 100 120 30 0 0 -- 0 60 -- 30 30 10 0 0 -- 0 -- 0 0 0 1.5 1.5 1.5 -- 1.5 1.5 10 0 60 -- -- -- -- -- 60 60 20 -- -- 60 -- -- -- 220 -- 180 -- 100 300 40 40 3.5 3.5 3.5 100 -- -- -- -- 5V 16.67 MHz Min Max -- 30 -- 50 0 -- 3 30 15 -- 3 15 120 50 60 15 0 0 -- 0 30 -- 15 15 5 0 0 -- 0 -- 0 0 0 1.5 1.5 1.5 -- 1.5 1.5 5 0 30 -- -- -- -- -- 30 30 10 -- -- 30 -- -- -- 110 -- 90 -- 50 150 20 20 3.5 3.5 3.5 50 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clks Clks Clks ns Clks Clks ns ns 22 MC68307 TECHNICAL INFORMATION MOTOROLA PRELIMINARY AC TIMING SPECIFICATIONS (VCC = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc; TA = TL to TH) (See Figures 8-10) Num 55 56e 57 58 NOTES: Characteristic R/W asserted to data bus impedance change HALT/RESET pulse width BGACK negated to AS, CSx, LDS, UDS, R/W driven BR negated to AS, CSx, LDS, UDS, R/W driven 3.3V 8.33 MHz Min Max 40 -- 10 -- 1.5 -- 1.5 -- 5V 16.67 MHz Min Max 20 -- 10 -- 1.5 -- 1.5 -- Unit ns Clks Clks Clks a. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns. b. Actual value depends on clock period. c. When AS, CSx and R/W are equally loaded (20%), subtract 5 ns from the values given in these columns. d. If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. e. For power-up, the MC68307 must be held in the reset state for 128 clock cycles after CLK and VCC become stable to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the controller. . MOTOROLA MC68307 TECHNICAL INFORMATION 23 S0 CLK S1 S2 S3 S4 S5 S6 S7 8 6 A23-A1 12 CSx, AS 13 11A LDS / UDS 9 15 11 14 R/W 47 DTACK 27 31 D15-D0 47 BR (NOTE 2) 47 32 HALT / RESET 56 47 ASYNCHRONOUS INPUTS (NOTE 1) 47 32 28 29 29A NOTES: 1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK) guarantees their recognition at the next falling edge of the clock. 2. BR need fall at this time only to ensure being recognized at the end of the bus cycle. Figure 8. Read Cycle Timing Diagram 24 MC68307 TECHNICAL INFORMATION MOTOROLA S0 CLK S1 S2 S3 S4 S5 S6 S7 8 6 A23-A1 21 CSx, AS (NOTE 2) 15 9 11 11A LDS / UDS 20A 17 18 22 R/W (NOTE 2) 20 9 14A 14 12 13 15A 47 28 DTACK 7 D15-D0 55 26 23 48 53 25 47 BR (NOTE 3) 47 32 HALT / RESET 56 47 ASYNCHRONOUS INPUTS (NOTE 1) 47 32 NOTES: 1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK) guarantees their recognition at the next falling edge of the clock. 2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge of S2 (specification #20A). 3. BR need fall at this time only to ensure being recognized at the end of the bus cycle. Figure 9. Write Cycle Timing Diagram MOTOROLA MC68307 TECHNICAL INFORMATION 25 CLK Strobes and R/W BR 37 46 35 34 39 36 BGACK BG 33 38 Figure 10. Bus Arbitration Timing PRELIMINARY 8051 BUS INTERFACE MODULE AC ELECTRICAL SPECIFICATIONS (VCC = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc; TA = TL to TH) (See Figures 11 and 12) Symbol tcyc TLHLL TAVLL TLLAX TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH NOTE: a. Wait states can be added. Cycle time ALE pulse width Address valid to ALE low Address hold after ALE low RD pulse widtha WR pulse width(1) in(1) RD low to valid data Data hold after RD Data float after RD Characteristic Min 120 2 x tcyc - 40 tcyc - 40 tcyc - 35 5 x tcyc 5 x tcyc -- 0 -- -- -- 3 x tcyc- 50 4 x tcyc - 130 tcyc - 60 7 x tcyc- 150 tcyc- 50 -- tcyc- 40 3.3V 8 MHz Max -- -- -- -- -- -- 5 x tcyc - 165 -- 0.5 x tcyc 8 x tcyc - 150 9 x tcyc - 165 3 x tcyc + 50 -- -- -- -- -- tcyc+ 50 5V 16.67 MHz Min Max 60 -- 2 x tcyc - 40 tcyc - 40 tcyc - 35 5 x tcyc 5 x tcyc -- 0 -- -- -- 3 x tcyc- 50 4 x tcyc - 130 tcyc - 60 7 x tcyc- 150 tcyc- 50 -- tcyc- 40 -- -- -- --8051 -- 5 x tcyc - 165 -- 0.5 x tcyc 8 x tcyc - 150 9 x tcyc - 165 3 x tcyc + 50 -- -- -- -- -- tcyc+ 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ALE low to valid data in(1) Address to valid data in(1) ALE low to RD or WR low Address to RD low or WR low Data valid to WR transition Data valid to WR Data held after WR high(1) RD low to address float RD or WR high to ALE high 26 MC68307 TECHNICAL INFORMATION MOTOROLA ALE TLHLL TLLDV TLLWL TRLRH TWHLH RD TLLAX TAVLL TRLDV TRHDZ TRHDX Data in TRLAZ TAVWL TAVDV Address AD7 - AD0 Address A23-A8 Figure 11. External Dat3a Memory Read Cycle ALE TLHLL TWHLH TLLWL TWLWH WR TLLAX TAVLL TQVWH Address Data out TQVWX TAVWL Address TWHQX AD7-AD0 A23-A8 Figure 12. External Data Memory Write Cycle MOTOROLA MC68307 TECHNICAL INFORMATION 27 PRELIMINARY IEEE 1149.1 ELECTRICAL SPECIFICATIONS (VCC = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc; TA = TL to TH) (See Figures 13-15) Num Characteristic TCK frequency of operation TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST width low 3.3V 8 MHz Min Max 0 10.0 100 -- 45 -- 0 5 15 -- 15 -- 0 80 0 80 15 -- 15 -- 0 30 0 30 80 -- 5V 16.67 MHz Min Max 0 10.0 100 -- 45 -- 0 5 15 -- 15 -- 0 80 0 80 15 -- 15 -- 0 30 0 30 80 -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns 1 2 3 6 7 8 9 10 11 12 13 14 1 3 2 VIH VIL 3 2 TCK Figure 13. Test Clock Input Timing Diagram TCK VIH VIL 6 7 Data inputs 8 Input data valid Data outputs 9 Output data valid Data outputs 8 Data outputs Output data valid Figure 14. Boundary Scan Timing Diagram 28 MC68307 TECHNICAL INFORMATION MOTOROLA TCLK VIH VIL 10 11 TDI TMS 12 Input data valid TDO 13 Output data valid TDO 12 TDO Output data valid Figure 15. Test Access Port Timing Diagram PRELIMINARY TIMER MODULE ELECTRICAL SPECIFICATIONS (VCC = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc; TA = TL to TH) (See Figure 16) 3.3V 5V 8 MHz 16.67 MHz Unit Min Max Min Max 1 Timer input capture pulse width 100 -- 50 -- ns 2 TINclock low pulse width 100 -- 50 -- ns 3 TIN clock high pulse width and input capture high pulse width 2 -- 2 -- Clk 4 TIN clock cycle time 3 -- 3 -- Clk 5 Clock high to TOUT valid -- 70 -- 35 ns NOTE: The TIN specifications do not apply to the use of TIN1 as a baud rate generator input clock. In such a case, specifications may be used. Num Characteristic Clock 0 5 TOUT (output) TIN (input) 2 4 1 3 Figure 16. Timer Module Timing Diagram MOTOROLA MC68307 TECHNICAL INFORMATION 29 PRELIMINARY UART ELECTRICAL SPECIFICATIONS (VCC = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc; TA = TL to TH) (See Figures 17 and 18) Num 1 2 3 Characteristic TxD output valid from TxC low RxD data setup time to RxC high RxD data hold time from RxC high 3.3V 8 MHz Min Max -- 700 480 -- 400 -- 5V 16.67 MHz Min Max -- 350 240 -- 200 -- Unit ns ns ns 1 bit time (1 or 16 clocks) Clock 1 TxD Figure 17. Transmitter Timing Clock 1X 2 3 RxD Figure 18. Receiver Timing 30 MC68307 TECHNICAL INFORMATION MOTOROLA PRELIMINARY M-BUS INTERFACE INPUT SIGNAL TIMING (VCC = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc; TA = TL to TH) (See Figure 19) Num 1 2 3 4 5 6 7 8 9 Start condition hold time Clock low period SDA/SCL rise time Data hold time SDA/SCL fall time Clock high period Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Characteristic 3.3V 8 MHz Min Max 2 -- 4.7 -- 0 -- 4 500 2 2 -- 2 -- 600 -- -- -- -- 5V 16.67 MHz Min Max 2 -- 4.7 -- 0 -- 4 250 2 2 -- 1 -- 300 -- -- -- -- Unit Clk Clk s Clk ns Clk s Clk Clk PRELIMINARY M-BUS INTERFACE OUTPUT SIGNAL TIMING (VCC = 5.0V 0.5V or 3.3Vdc 0.3V; GND = 0Vdc; TA = TL to TH) (See Figure 19) Num 1 2 3 4 5 6 7 Start condition hold time Clock low period SDA/SCL rise time Data hold time SDA/SCL fall time Clock high period Data setup time Characteristic 3.3V 8 MHz Min Max 8 -- 11 -- 0 -- 11 (Spec 2) x Clk 20 20 -- 2 2 600 -- -- 5V 16.67 MHz Min Max 8 -- 11 -- 0 -- 11 (Spec 2) x Clk 10 10 -- 1 2 300 -- -- Unit Clk Clk s Clk ns Clk ns 8 9 Start condition setup time (for repeated start condition only) Stop condition setup time -- -- -- -- Clk Clk SDA 1 4 7 8 9 SCL 3 2 5 6 Figure 19. M-Bus Interface Input/Output Signal Timing MOTOROLA MC68307 TECHNICAL INFORMATION 31 MECHANICAL DATA The MC68307 is available in a 100-lead QFP package (FG suffix). Figure 20 shows the MC68307 pinout. Figure 21 shows the case drawing for the MC68307. 80 81 PB0/SCL PB1/SDA VCC PB2/TxD PB3/RxD PB4/RTS PB5/CTS PB6/TIN1 PB7/TIN2 PB8/INT1 PB9/INT2 PB10/INT3 GND PB11/INT4 PB12/INT5 PB13/INT6 PB14/INT7 PB15/INT8 VCC PA0/CS2B PA1/CS2C PA2/CS2D PA3/TOUT1 PA4/TOUT2 PA5/BR PA6/BG GND PA7/BGACK IRQ7 A23 51 50 79 52 TMS D15 D14 D13 D12 GND D11 D10 D9 D8 D7 D6 D5 D4 VCC D3 D2 D1 D0 TDO 100 1 MC68307 (TOP VIEW) A22 A21 A20 A19 A18 VCC A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7/AD7 A6/AD6 A5/AD5 31 30 32 TDI ALE RD GND WR AS UDS LDS R/W DTACK TRST/RSTIN VCC HALT RESET TCK CS0 CS1 CS2A/CS2 CS3 GND CLKOUT EXTAL XTAL BUSW A0/AD0 A1/AD1 A2/AD2 VCC A3/AD3 A4/AD4 Figure 20. MC68307 FG Suffix--Pinout MC68307 TECHNICAL INFORMATION MOTOROLA MC68307FG CASE 842B-01 0.20 M Y H A-B S D S 80 81 50 AA 51 0.20 (0.008) 0.05 (0.002) M C A-B S D S A-B A V L DETAIL "A" 31 B B 100 Z 1 D A S 30 0.20 (0.008) M C A - B S D S 0.05 (0.002) A - B 0.20 (0.008) M H A-BS D S DETAIL "C" SECTION B-B B B F P U J A, B, D BASE METAL N DATUM PLANE 0.02 (0.008) M T H R K W X Q DETAIL "A" D C A-B S D S CE M DETAIL "C" DATUM PLANE H C SEATING PLANE H G INCHES MIN MAX 0.783 0.791 0.547 0.555 -- 0.130 0.009 0.015 0.100 0.120 0.009 0.013 .0.026 BSC 0.004 0.014 0.007 0.009 0.026 0.037 .0.486 REF 16 5 0.005 0.007 .0.013 BSC 0 7 0.010 0.014 0.931 0.951 0.005 -- -- 0 0.695 0.715 -- 0.016 0.007 REF 0.023 REF 0.033 REF 0.742 REF 0.1 (0.004 ) M DIM A B C D E F G H J K L M N P Q R S T U V W X Y Z AA MILLIMETERS MIN MAX 20.10 19.90 13.90 14.10 -- 3.30 0.38 0.22 2.55 3.05 0.22 0.33 .0.65 BSC 0.10 0.36 0.17 0.23 0.65 0.95 12.35 REF 5 16 0.17 0.13 0.325 BSC 0 7 0.25 0.35 23.65 24.15 -- 0.13 -- 0 17.65 18.15 0.40 -- 1.95 REF 0.58 REF 0.83 REF 18.85 REF NOTES: 1. DUE TO SPACE LIMITATION, CASE 842B-01 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 100 LEADS. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. CONTROLLING DIMENSION: MILLIMETER. INCHES ARE IN "( )". 4. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 5. DATUMS -A-, -B-, AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 6. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 7. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 8. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. Figure 21. MC68307 FG Suffix--Package Dimensions MOTOROLA MC68307 TECHNICAL INFORMATION 33 MORE INFORMATION The documents listed in the following table contain detailed information on the MC68307. These documents may be obtained from the Literature Distribution Centers at the addresses listed below. Table 12. Documentation Document Title Order Number BR1114/D MC68307UM/AD M68000PM/AD BR729/D Contents M68300 Family Overview Detailed information for design M68000 Family Instruction Set Independent vendor listing supporting software and development tools M68300 Integrated Processor Family MC68307 User's Manual M68000 Family Programmer's Reference Manual The 68K Source Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. |
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